1. Field
Embodiments relate to a semiconductor device fabrication technology, and more particularly, to a nonvolatile memory device and a method for fabricating the same.
2. Description of the Related Art
A life environment is being changed such that anyone can conveniently use desired information anytime and anywhere, thanks to recently developed digital media devices. A variety of rapidly spreading digital devices require storage media capable of conveniently storing captured images, recorded music and various data. In order to meet this requirement, there is a growing interest in the field of a system-on-chip (SoC) according to a trend towards a high degree of integration of non-memory semiconductors, and semiconductor manufacturers compete to invest in the field of SoC in an effort to strengthen SoC-based technology. A SoC refers to system technologies that are integrated in one semiconductor. If a system design technology is not secured, it may be difficult to develop non-memory semiconductors.
A type of SoC where complicated technologies are integrated, is an embedded memory. A memory which is highlighted among embedded memories is a flash memory. Flash memory may be divided into a NOR type and a NAND type. A NOR type flash memory is mainly used in embedded memories. Also, a flash memory may be divided into a floating gate type and a silicon-oxide-nitride-oxide-silicon (SONOS) type. Recently, research has been actively conducted for the SONOS type.
FIG. 1 is a cross-sectional view illustrating a conventional nonvolatile memory device.
Describing a conventional SONOS type flash memory device with reference to FIG. 1, a memory gate (MG) in which a memory layer 105 and a gate electrode 106 are stacked is formed on a substrate 101, and spacers 107 are formed on both sidewalls of the memory gate MG. Source/drain regions 108 are formed in the substrate 101 on both sides of the memory gate MG. The memory layer 105 is an oxide-nitride-oxide (ONO) layer in which a first oxide layer 102, a nitride layer 103 and a second oxide layer 104 are sequentially stacked. The gate electrode 106 serves as a control gate.
In the flash memory device having the above structure, a problem may be caused in that over-erase is likely to occur in an erase operation. In order to solve this problem, an additional operation such as recovery is used, and due to this fact, the size of a peripheral circuit may increase.
Further, while the conventional flash memory device uses a hot carrier injection (HCI) scheme for a program operation, since the HCI scheme consumes a large amount of current for programming, the HCI scheme is inappropriate for an embedded memory.